Crosstalk results when a photogenerated carrier, say an electron, is generated beyond the depletion region beneath one photodiode or another photosensitive region, and the electron diffuses and/or drifts away and is collected by another photodiode or another photosensitive region. For clarity, photodiodes will be used as examples and the image sensor is assumed to be an array of pixels. Crosstalk by electrons reduces the modulation transfer function and mixes colors. Thus, it is desirable to reduce and/or eliminate such crosstalk.
Many image sensors based on charge-coupled devices (CCDs) are made in an n-epitaxial silicon layer on an n-type silicon substrate wafer. These imagers usually utilize a vertical overflow drain, which prevents electrons generated beyond the vertical overflow drain from reaching the photodiodes. Other image sensors are built in a p-epitaxial silicon layer on a heavily doped p-type silicon substrate. These p/p+ wafers are favored by silicon foundries for CMOS circuits. Thus, CMOS image sensors are usually made in p/p+ wafers to take advantage of the mainstream CMOS processes and circuits. Imagers made in p/p+ wafers lack the vertical overflow drain, so other methods have been tried. For example, U.S. Pat. No. 5,859,462, assigned to Eastman Kodak Company, teaches several crosstalk reduction schemes. Image sensor customers are presently demanding even more crosstalk reduction, so new approaches are needed. Various approaches have been tried with p/p+ wafers at CMOS foundries, but to date none has been sufficiently effective. Dongbu Electronics in U.S. Pat. No. 6,897,500 claims crosstalk reduction through an isolation layer surrounding each pixel. Such a structure consumes silicon area and is difficult to scale to smaller pixels. Thomson-CSF has patented a patterned subcollector method aimed at anti-blooming rather than crosstalk—U.S. Pat. Nos. 4,916,501 and 4,997,784. This approach is not as effective as the method proposed here and, in fact, part of the subcollector enhances the diffusion of electrons to other pixels. U.S. Pat. No. 6,225,670 suggests a method involving a potential barrier and lateral flow.
The present invention would reduce the number of photogenerated electrons that originate under one photodiode and diffuse and/or drift to another photodiode. This reduces the crosstalk. The invention introduces a buried n-doped region in a p-type epitaxial silicon layer on a p+ silicon substrate. The resulting pn junction is contacted and biased. A second p-type epitaxial silicon layer is deposited over the first p-epitaxial layer after the n-type dopant has been introduced. The pn junction collects the diffusing electrons and prevents them from reaching other photodiodes. The contact to the buried n-region is constructed within the second p-epitaxial layer. The CMOS circuits are built in the p-epitaxial/p-epitaxial/p+ substrate, i.e., the regions without the buried n-region, so the wafer is compatible with the standard CMOS offered by a foundry. In addition, this takes advantage of the excellent gettering of p/p+ substrates to reduce the metal concentrations in the device regions. The gettering lowers dark current and point defects.